1. Field of the Invention
The present invention relates to PCM telecommunication facilities, especially PCM long distance exchange facilities with several synchronous pulse clock controlled transmitters having a common transmitter channel.
2. Description of the Prior Art
In telecommunication facilities the problem frequently presents itself that of several peripheral devices which share a common central device to be used together, at any given time no more than one such peripheral device can be in the position to establish connection with the central device. In the known prior art, a variety of selection circuits are known in the form of selectors, relays, chain circuits and other similar electronic switching techniques. In this connection the self-blocking test multiplex is known.
The present invention relates specifically to a circuit for PCM telecommunication facilities, especially PCM long distance exchange facilities in which several synchronous pulse clock controlled transmitters for the transmission of binary coded information have simultaneous access to a common transmission channel and in which two or more simultaneous transmission processes are eliminated after simultaneous starts of two of a plurality of different transmitters. The following conditions are present:
(a) each one transmitter initially always at the beginning of a transmission process transmits its own binary coded transmitter specific address; PA1 (b) the information transmitted by the transmitters flows together bitwise as far as they are transmitted by two or more transmitters simultaneously; PA1 (c) with inequality of binary characters transmitted in their coequal time-slot by two or more transmitters and flowing together always the character of the one kind of the two possible kinds of binary characters maintains itself compared to the character of the other kind; PA1 (d) the information flowing together is fed back to the transmitters; PA1 (e) each transmitter compares the information transmitted instantaneously with the instantaneously received information bit by bit; and PA1 (f) for each transmitter the instantaneously received character is the one kind, however, the one transmitted by its time-slot coequal which is of the other kind, interrupts its transmission.
A circuit arrangement of this kind for addressing the above conditions is already known through the recommendations in the Redbook of the CCITT. In circuits of this nature, for each transmitter the possibility of access to a common transmission channel is given through the capability of each transmitting channel to start transmission over the common transmitting channel. When transmission by one transmitter is in progress, transmission by another transmitter must be avoided. This can be ensured in ways known in the art in that a transmission process in progress is signalled to all transmitters by which each one is prevented to start a transmission process. The difficulty of this prior art is in the recognition of the simultaneous start of two transmitting processes and the corresponding prevention. For this purpose, in circuit arrangements of the known prior art, the binary character being on the transmitting channel in the process of being transmitted is transferred backwards and supplied back to the transmitters of which each transmitter transmitting at the time compares this binary character received back instananeously with the instantaneous binary character actually brought by itself to the point of being transmitted--which means only by it--. As soon as a transmitter recognizes hereby a difference between the instantaneous binary character transmitted by itself and the instantaneous binary character coming to transmission over the transmitting channel, it interrupts, even while in progress binary character transmission. Up to this point, no binary character falsification can have taken place on the transmitting channel.
In order to prevent in a circuit arrangement of the known prior art a binary character falsification with certainty, it is required that the interruption mentioned before of the transmitting process of that transmitter which has recognized the binary character difference takes place in time, so that the start of a binary character falsification for the next binary character is prevented with some certainty.
This timeliness of the interruption of one of two accidentally simultaneously started transmission processes is a problem, the solution of which is fundamental to the invention.
In the case of a circuit arrangement of the known prior art no preparatory selection before the occupation of the transmitting channel through one of the several transmitters of one of possibly two or several transmissions, which at the same time are ready to start transmission, takes place. Such a selection is at the beginning of each transmitting process.
To prevent the start of the transmission process of a transmitter before another transmission process of another transmitter has commenced to transmit, is--as already mentioned still relatively easy to do and known in the prior art. However, to avoid having a simultaneous transmitter start with respect to the common pulse clock control turn into a falsification of information transmitted over the common transmitting channel, the known measure is to have each transmitter begin a new transmitting process always with the transmission of its binary coded transmission specific address. Independently of that, it can additionally be provided that a transmitter checks before transmission begins if a transmission process of another transmitter is in progress; however, with such a check the case of an accidental simultaneous transmission start does not register. Through transmission of its own binary coded address of each transmitter at the beginning of the transmission of the actual message, it becomes possible to prevent a pulse timed accidental simulataneous start of the transmission of two transmitters and, thus, preclude information falsification. For the prevention of information falsification, the previously indicated passing of one character of one kind of two binary characters is compared to a pulse timed synchronous character of the other kind as well to the comparison done per transmitter and per character of the character transmitted by that particular transmitter with the actual instantaneous character present on the transmitting channel. If two transmitters have started pulse timed synchronous transmission, then there always appears in the first transmission of the transmitter a specific binary coded address, with certainty at least in one bit of the several synchronous transmitted binary characters. These addresses by necessity have a character inequality with respect to the binary character transmitted by it and the binary character state existing instantaneously on the transmitting channel. This character inequality is only recognized through the comparison of that transmitter (and only through that, not through the other transmitter) which with this particular bit transmits the character of the mentioned other kind; thus, the character compared to the character of the mentioned one kind is inferior, that is, the binary character which does not assert itself. The transmitter recognizing the character inequality immediately interrupts its transmission process while the other transmitter continues its transmission process without having even noticed these transient transmission paralleleties and without a character falsification in the binary character transmitted. However, this interruption of the transmission process on the part of the particular transmitter must have taken place even before the start of the subsequent binary character so that this is not affected by a character falsification during one of the subsequent pulse measurements. This is the problem of timeliness.
The principle of the undirectional character as explained, presupposes a use of appropriate gate circuits with OR conditions. In known circuit arrangements of the kind of which the most significant characteristics were indicated, OR gates are used as for instance in the Nachrichtentechnische Zeitschrift 1957, 6, page 251, picture 9 and in the technical book "Das TTL Kpchbuch" published by Texas Instruments, Germany GmbH, applications labor, 805 Friesing edition TM 650/1172, 1st edition (Nov. 1972) pages 116, 306 and 317 ("Open Collector"). At the output side they transmit one of the two possible binary characters relatively low ohmicly, that is, not over a series resistance or over a line with a relatively low resistance value. The other of the two possible binary characters, however, are transmitted over a resistance, the value of which has to be large enough in view of a transmission of the first mentioned possible binary character. This means, however, for a transmission of the mentioned other binary character that it is transmitted over this resistance while the first mentioned binary character in comparison is transmitted relatively low ohmicly. This has, as a consequence, a capacitive line influences of the transmitting channel as well as unidirectional delays in the character transfer in signal paths leading to it and thus of distortions and therefore the danger of the character falsification whereby the binary character of the one kind and characters of the other kind are affected differently by these delays which increases the falsification effect.
With an arrangement of the known prior art further technical problems result if as has been considered above, two or more transmission processes accidentally start in equal time-slots. If a binary character of the one kind and another binary character of the other kind flow together on the transmission channel whereby the one single character first transmitted should assert itself against the several latter, transmitted characters then binary characters of the other kind with respect to its amplitude and/or pulse shape cause a character falsification leading to a transmission error.
If gate circuits of the known kind in the known manner are used, problems of transmission certainty with respect to the accuracy of the transmitted binary characters will result. At the same time, however, the problem of timeliness will result in a possible interruption of a transmission process because of the demand that two binary characters transmitted simultaneous and merged need to traverse the path from the particular two transmitters to the transmitting channel quickly enough, and back to the transmitters so that in one of them the transmission process is interrupted such that no character falsification occurs.
The present invention is designed to create an improved circuit arrangement over that of the prior art with more favorable conditions for the character transmission with respect to the transmission rate and the prevention of character falsification and to ensure thereby a timely interruption of a transmission process when such an interruption is necessary.